The present invention relates to a semiconductor integrated circuit technique for addressing increase in speed of external output operation synchronized with a clock signal. More particularly, the invention relates to, for example, a semiconductor integrated circuit using, in an external interface portion, a MOS transistor having a breakdown voltage higher than that of an internal circuit and, further, to a technique effective to be applied to a burn-in method of such a semiconductor integrated circuit.
Japanese Unexamined Patent Application No. 9(1996)-8632 discloses a technique of stepping down an external power supply voltage within an LSI and making an external interface circuit operate with an external power supply voltage by using the stepped-down voltage as an operation power source of an internal circuit from a viewpoint of reduction in the size of a circuit device, reduction in power consumption, and the like. Japanese Unexamined Patent Application No. 2000-353947 discloses a technique in a semiconductor output circuit having a function of shifting the level of an internal signal to a signal level of a breakdown voltage of a semiconductor device or higher and outputting the resultant, and a function of outputting a signal at the internal signal level which is before the level shifting. In the semiconductor output circuit, for an output buffer in which a MOS transistor for protection used to increase a breakdown voltage between the gate and source of an output buffer transistor is provided on the power supply side, in order to prevent delay in speed of change in rising of a signal caused by on-state resistance of the MOS transistor for protection (the power supply voltage of the output buffer is the same as that in the internal circuit), the on-state resistance of the MOS transistor for protection is set to be varied by controlling a gate voltage.